I. Field of the Disclosure
The technology of the disclosure relates generally to clock trees in integrated circuits.
II. Background
Mobile communications devices have become common in current society. The prevalence of these mobile devices is driven in part by the many functions that are now enabled on such devices. Demand for such functions increases processing capability requirements and generates a need for more powerful batteries. Within the limited space of the housing of the mobile communications device, batteries compete with the processing circuitry. The limited space contributes pressure to continued miniaturization of components. Likewise, the limited space available for batteries contributes pressure to reduce power consumption by the circuitry. While miniaturization and power consumption have been of particular concern in the integrated circuits (ICs) of mobile communications devices, other ICs have also been impacted.
Historically, elements within an IC have all been placed in a single two-dimensional (2D) active layer with elements interconnected through one or more metal layers that are also within the IC. For more complex circuit requirements, multiple ICs are interconnected through conductors on a printed circuit board. While such circuits have generally become smaller according to Moore's Law, efforts to miniaturize ICs are reaching their limits in a 2D space and thus, design thoughts have moved to three dimensions. While there have been efforts to connect two or more ICs through a separate set of metal layers outside the IC proper, that solution is not properly a three-dimensional (3D) approach. Likewise, two IC chips have been stacked one atop of another with connections made between the two IC chips through solder bumps (i.e., the so called “flip chip” format). Likewise, there are system in package (SiP) solutions that stack IC chips atop of one another with connections made between the chips with through silicon vias (TSVs). While arguably the flip chip and TSV aspects represent 3D solutions, the amount of space required to effectuate a flip chip remains large. Likewise, the space required to implement a TSV relative to the overall size of the chip becomes space prohibitive if many TSVs are required. The best 3D solution to date is seen in the evolution of monolithic three-dimensional ICs (3DICs).
The advent of monolithic 3DICs has provided a number of interesting possibilities in circuit design, but creates its own design issues especially as it relates to clock management. Of particular concern is clock skew, which is the time difference in the arrival of an edge of a clock signal at two different elements that rely on the clock signal (e.g., a latch or flop). Clock skew is of concern because it reduces the effective clock period available for computation. In 2D designs, clock skew arises primarily from delay created by intervening conductive paths of different lengths. Some clock skew may arise from process variations between elements. Additional clock skew may result from clock uncertainty. While an annoyance in a 2D design, such annoyances are exacerbated into legitimate problems in a 3D design. Not only may there be process variations within a single tier, there may be process variations between different dies or different tiers. Likewise, the conductive paths may have dramatically different lengths between tiers (e.g., paths on the tier with the clock source may be substantially shorter than paths that extend to another tier). Accordingly, there is a need to provide clock management regimes in 3DICs.